Traditional CMOS (complementary metal oxide semiconductor) techniques include process flows for constructing planar FET devices. With planar FETs, increased transistor density can be achieved by decreasing the pitch between transistor gate elements. However, with planar FET devices, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to vertical FET devices, which decouple the gate length from the gate pitch requirement and enable scaling of transistor density. In general, vertical FET devices are designed to have gate structures that are formed on multiple sides of a vertical channel structure (e.g., a vertical semiconductor fin or vertical nanowire). In addition, vertical FET devices employ doped source and drain regions, wherein a doped source region can be formed on top of a vertical semiconductor fin, and wherein a doped drain region can be formed underneath the vertical semiconductor fin. With vertical FET devices, scaling is determined by how close vertical conductive contacts to the source and drain regions can be placed.
One challenge with vertical FET fabrication involves the formation of bottom insulating spacers to insulate the lower source/drain regions from the gate structures. For example, some fabrication techniques involve depositing a layer of insulating material (e.g., oxide material) to cover the lower source/drain regions, followed by an etch-back process to remove the excess insulating material and form the bottom insulating spacers. The etch-back process typically results in the formation of a meniscus-shaped (curve-shaped) upper surface of the bottom insulating spacer, wherein end portions of the bottom insulating spacer, which are adjacent to and in contact with sidewalls of vertical semiconductor fins, curve slightly upward along the sidewalls of the vertical semiconductor fins. The curved upper surfaces of the bottom insulating spacers against the lower sidewalls of vertical semiconductor fins results in insulating material being disposed between a lower portion of a gate structure and the semiconductor fin, which undesirably reduces the gate length and, consequently, leads to issues of gate controllability. Furthermore, the etch-back process can result in over etching of the thickness of the bottom insulating spacer, resulting in thinner than expected bottom insulating spacers, which increases the parasitic capacitance between the lower source/drain regions and the gate structures. These structural anomalies lead to reduced electrostatic control of the operation of the vertical FET devices.